The present invention relates to a semiconductor device, and more particularly to an EEPROM (Electrically Erasable and Programmable ROM) semiconductor storage device incorporating a boosting circuit.
A high voltage is required for write/erase of data for the cells of a semiconductor storage device such as an EEPROM. But, incorporating a boosting circuit in the device makes it unnecessary to provide a high voltage source externally. Thus, the voltage supplied from a certain external voltage source can be boosted to a desired minus or plus voltage. In this case, whether or not a desired potential has been generated can be decided by monitoring it using a detection circuit. For example, a conventional DINOR (Divided bit-line NOR) type flash memory, disclosed in 1992 IEDM TECHNICAL DIGEST pp. 599-602 "A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VOLT OPERATION, SECTOR ERASE FLASH MEMORY" 1995 ISSCC DIGEST OF TECHNICAL PAPERS "A 3.3 v-Only 16 Mb DINOR RECEIVED flash Memory", has a circuit configuration for boosting and detecting.
As shown in FIG. 15, the potentials generated from boosting circuits 1a and 1b are connected to a resistor 3 of the detection circuit 2. The potential at a prescribed position of the flash memory is detected by a detecting section 4.
In the DINOR type flash memory, the potentials of 10 V and -8 V are generated by boosting circuits 1a and 1b from a single external power supply voltage (not shown). For example, assuming that the connecting points between the boosting circuits 1a, 1b and the resistor 3 are A and B, respectively, when the potential at the detecting point 4 provided at the point dividing the segment between A and B at a ratio of 8.5:9.5 is 1.5 V, it is recognized that a desired potential has been generated.
The resistor 3 used in such a detecting circuit is made of the same material used when the floating gate and control gate constituting a memory cell is fabricated.
In order to prevent the boosted potential in the boosting circuits 1a, 1b, from being reduced, the detecting circuit 2 is required to suppress power consumption and prevent surplus current leakage from the boosting circuits 1a, 1b. This requires that the resistance of the resistor 3 be relatively large so that the current flowing to the detecting circuit 2 is small.
However, since the resistor 3 used in the detection circuit 2 of the conventional EEPROM is made of the same material as that of a floating gate or control gate, it is made of a polysilicon film or a polycide film, i.e., a laminated film composed of a polysilicon film and a refractory metal suicide film. For this reason, the floating gate made of a polysilicon film with a small sheet resistance, e.g., with a thickness of 100 nm and boron impurity concentration of 7E20/cm.sup.3 has a small sheet resistance of about 70 .OMEGA./.sup.H.sub.T. The control gate made of a polycide film of a WSi film of 100 nm and a polysilicon film of 100 nm used as a word line of the memory cell has a very small sheet resistance of about 12 .OMEGA./.sup.H.sub.T.
Thus, the resistor 3, which is made of a material having a small sheet resistance, leads to an increase in the area for assuring adequate resistance and hence is not suitable for the requirements of miniaturization and high-integration of recent years.
In the resistor 3 made of the polysilicon of the floating gate, when the oxide film on the polysilicon film is etched for connection to the boosting circuits 1a, 1b and the detecting point to form a connecting hole, because of over-etching, the connecting hole might penetrate through the polysilicon, as shown in FIG. 16. In FIG. 16, 3a denotes the polysilicon of the floating gate constituting the resistor 3; 5 denotes a semiconductor substrate (hereinafter referred to as "substrate"); 6 denotes a field oxide film formed on the substrate 5; 7 denotes an oxide film formed on the polysilicon film 3a; 8 denotes a connecting hole formed in the oxide film; and 9 denotes a wiring layer connected to the polysilicon film 3a.
The polysilicon film 3a of the floating gate is a thin film having a thickness of e.g. 100 nm or so, and is thin particularly on the field oxide film 6 because of the variation in the film thickness. Therefore, as shown in FIG. 16, when the connecting hole 8 is formed, because of over-etching, punch-through may easily occur in the polysilicon film 3a. The contact resistance with the wiring layer 9 to be formed in the subsequent step may increase. Further, since the underlying field oxide film 6 is easily etched, the hole may partially reach the underlying substrate 5 (not shown). In this case, the polysilicon film 3a and the substrate 5 may be short-circuited.